The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Aug. 30, 2019
Applicant:

Ademco Inc., Golden Valley, MN (US);

Inventors:

Jesus Omar Ponce, Chihuahua, MX;

Luis Carlos Murillo, Chihauhua, MX;

Cesar Alejandro Arzate, Chihuahua, MX;

Eduardo Saenz Balderrama, Chihuahua, MX;

Assignee:

Ademco Inc., Golden Valley, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); F24F 11/88 (2018.01);
U.S. Cl.
CPC ...
H03K 19/017554 (2013.01); F24F 11/88 (2018.01); H03K 19/0175 (2013.01); H03K 19/017518 (2013.01);
Abstract

A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.


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