The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Apr. 27, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Michael Kevin Batenburg, San Diego, CA (US);

Vincent Pierre Le Roy, San Diego, CA (US);

Praveen Kumar Origanti, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 11/00 (2006.01); G01R 31/00 (2006.01); G01R 21/00 (2006.01); G01R 25/00 (2006.01); G01R 27/28 (2006.01); H02H 3/20 (2006.01); H02H 3/05 (2006.01); H02J 9/00 (2006.01); H02J 9/06 (2006.01); H02H 1/00 (2006.01); G01R 19/165 (2006.01); G06F 1/28 (2006.01);
U.S. Cl.
CPC ...
H02H 3/20 (2013.01); G01R 19/165 (2013.01); G06F 1/28 (2013.01); G06F 17/5009 (2013.01); H02H 1/0007 (2013.01); H02H 3/05 (2013.01); H02J 9/061 (2013.01); G06F 11/00 (2013.01); G06F 13/10 (2013.01); G06F 13/12 (2013.01); G06F 17/5081 (2013.01); G06F 2217/14 (2013.01); G06F 2217/78 (2013.01);
Abstract

In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.


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