The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Aug. 31, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Toshiya Yonehara, Kawasaki, JP;

Tatsuo Shimizu, Shinagawa, JP;

Hiroshi Ono, Setagaya, JP;

Daimotsu Kato, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/778 (2013.01); H01L 23/5329 (2013.01); H01L 29/0649 (2013.01); H01L 29/40111 (2019.08); H01L 29/41725 (2013.01); H01L 29/4232 (2013.01); H01L 29/42352 (2013.01); H01L 29/4966 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/7786 (2013.01); H01L 29/78391 (2014.09); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/42336 (2013.01); H01L 29/513 (2013.01);
Abstract

In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.


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