The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jul. 01, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sung Gil Kim, Yongin-si, KR;

Seul Ye Kim, Seoul, KR;

Hong Suk Kim, Yongin-si, KR;

Jin Tae Noh, Yongin-si, KR;

Ji Hoon Choi, Seongnam-si, KR;

Jae Young Ahn, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/532 (2006.01); H01L 27/108 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 25/065 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/53295 (2013.01); H01L 24/29 (2013.01); H01L 25/065 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/11565 (2013.01); H01L 29/0649 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.


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