The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2020
Filed:
Mar. 21, 2018
Qualcomm Incorporated, San Diego, CA (US);
Seid Hadi Rasouli, San Diego, CA (US);
Michael Joseph Brunolli, Escondido, CA (US);
Christine Sung-An Hau-Riege, Fremont, CA (US);
Mickael Malabry, San Diego, CA (US);
Sucheta Kumar Harish, San Diego, CA (US);
Prathiba Balasubramanian, Chennai, IN;
Kamesh Medisetti, Bangalore, IN;
Nikolay Bomshtein, San Diego, CA (US);
Animesh Datta, San Diego, CA (US);
Ohsang Kwon, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.