The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jun. 12, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Haitao Cheng, San Diego, CA (US);

Zhang Jin, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H03H 1/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/528 (2013.01); H01L 23/5227 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H03H 1/0007 (2013.01); H03H 2001/0021 (2013.01);
Abstract

An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.


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