The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Aug. 20, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ju-Ho Jeon, Bucheon-si, KR;

Han-Gi Jung, Hwaseong-si, KR;

Hun-Dae Choi, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); H03L 7/081 (2006.01); H03L 7/08 (2006.01); G11C 29/50 (2006.01); H03K 21/02 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/50012 (2013.01); H03K 21/02 (2013.01); H03L 7/0802 (2013.01); H03L 7/0812 (2013.01); G11C 2207/2272 (2013.01);
Abstract

A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.


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