The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2020
Filed:
Nov. 14, 2018
A.u. Vista Inc., Milpitas, CA (US);
Ming-Hsien Lee, Hsinchu, TW;
Fang-Chen Luo, Milpitas, CA (US);
A.U. VISTA INC., Milpitas, CA (US);
Abstract
A representative display system includes: a pixel array having a plurality of pixels, gate lines, and data lines; a first of the pixels having a first TFT, a second TFT, a storage capacitor, and an LED; the first TFT having a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode coupled to a first of the gate lines, the first source electrode and the first drain electrode coupled between a first of the data lines and a first terminal of the storage capacitor; the second TFT having a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode coupled between the first TFT and the storage capacitor; the LED coupled to the second TFT; wherein the storage capacitor is configured to store a data voltage corresponding to a data signal, coupled to the first terminal, from the first of the data lines during an on-time of the first TFT; and wherein the LED is controllable to emit light at a brightness corresponding to duration of a driving current flowing through the LED, the driving current being provided to the LED in response to the data voltage from the storage capacitor and a PWM signal, coupled to a second terminal of the storage capacitor terminal and configured as a sawtooth waveform, being provided to the second gate electrode.