The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2020
Filed:
Oct. 18, 2017
Applicant:
Gsi Technology, Inc., Sunnyvale, CA (US);
Inventors:
Young-Nam Oh, San Jose, CA (US);
Soon Kyu Park, San Jose, CA (US);
Jae Hyeong Kim, San Ramon, CA (US);
Assignee:
GSI TECHNOLOGY, INC., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G06F 9/4401 (2018.01); G11C 7/22 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4097 (2006.01); G06F 1/10 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4403 (2013.01); G06F 1/10 (2013.01); G06F 1/26 (2013.01); G11C 5/148 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4097 (2013.01); G11C 2207/2227 (2013.01);
Abstract
A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.