The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jan. 10, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jong-lae Park, Anyang-si, KR;

Ju-hwan Kim, Hwaseong-si, KR;

Bum-gyu Park, Suwon-si, KR;

Dae-yeong Lee, Hwaseong-si, KR;

Dong-hyeon Ham, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/3287 (2019.01); G06F 1/3234 (2019.01); G06F 11/30 (2006.01); G06F 12/0811 (2016.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06F 1/3225 (2019.01); G06F 12/0806 (2016.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/324 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 11/3037 (2013.01); G06F 11/3062 (2013.01); G06F 12/0806 (2013.01); G06F 12/0811 (2013.01); G06F 2201/88 (2013.01); G06F 2201/885 (2013.01);
Abstract

An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.


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