The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jan. 26, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Jingang Hao, Beijing, CN;

Dongkun Wu, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 23/60 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136204 (2013.01); H01L 23/60 (2013.01); H01L 27/0248 (2013.01); H01L 27/1244 (2013.01); G02F 1/136286 (2013.01);
Abstract

An array substrate (), a fabrication method of the array substrate (), and a display panel and an electronic device having the array substrate () are provided. The array substrate () includes a base substrate (), and a gate line (), an insulating layer (), a data line (), and a first active pad layer () provided on the base substrate (); wherein, the insulating layer () is provided on the gate line (), the data line () is arranged on the gate line () through the insulating layer () and is arranged intersecting with the gate line (), the first active pad layer () is arranged on the gate line () through the insulating layer () and is arranged overlapping with the gate line (), and the first active pad layer () is arranged outside a region where the gate line () and the data line () overlap with each other.


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