The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2020
Filed:
Nov. 29, 2016
Fifth Electronics Research Institute of Ministry of Industry and Information Technology, Guangzhou, CN;
Yiqiang Chen, Guangzhou, CN;
Ang Li, Guangzhou, CN;
Dengyun Lei, Guangzhou, CN;
Yunfei En, Guangzhou, CN;
Lichao Hao, Guangzhou, CN;
Wenxiao Fang, Guangzhou, CN;
Bo Hou, Guangzhou, CN;
Abstract
An ESD failure early warning circuit for an integrated circuit is disclosed, including a positive voltage stress generation module, a negative voltage stress generation module, a buck module, a warning output module, capacitors C, C, and diodes D, D, D, Dand D. The ESD failure early warning circuit can report a warning timely when there is an ESD event in the monitored integrated circuit, to improve the reliability of the device effectively. Moreover, the stress voltage generated by the positive voltage stress generation module and the negative voltage stress generation module is adjustable, so the stress voltage can be set flexibly by a user according to actual condition of the monitored integrated circuit. The present invention has high flexibility and wide application prospect.