The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Sep. 30, 2016
Applicant:

Square, Inc., San Francisco, CA (US);

Inventors:

Mani Razaghi, San Francisco, CA (US);

Jesse Hill, Daly City, CA (US);

Assignee:

Square, Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/08 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 7/14 (2006.01); H05K 5/02 (2006.01); G01N 27/20 (2006.01); G01N 17/00 (2006.01); G01N 17/02 (2006.01); G01L 1/10 (2006.01); G01L 1/20 (2006.01); G01R 27/00 (2006.01); G01L 1/22 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0275 (2013.01); G01N 17/00 (2013.01); G01N 17/006 (2013.01); G01N 17/02 (2013.01); G01N 27/20 (2013.01); H05K 1/181 (2013.01); H05K 5/0217 (2013.01); H05K 7/1427 (2013.01); G01L 1/10 (2013.01); G01L 1/20 (2013.01); G01L 1/22 (2013.01); G01R 27/00 (2013.01); H05K 2201/10151 (2013.01);
Abstract

A payment reader includes a tamper detection system having a first sensor element disposed on a circuit board of the tamper detection circuit; a second sensor element disposed within an interior surface of a housing of the tamper detection circuit; and a guard ring disposed on the circuit board of the tamper detection circuit configured to form an electrical connection with the first sensor element in response to injection of conductive fluid thereby indicating tampering with the tamper detection circuit, wherein the guard ring is configured to be on a plane different from the first sensor element to prevent unintentional activation of the tamper detection circuit.


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