The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Feb. 06, 2018
Applicant:

Asustek Computer Inc., Taipei, TW;

Inventors:

Hank Lin, Taipei, TW;

Bin-Chyi Tseng, Taipei, TW;

Tsung-Chieh Yen, Taipei, TW;

Assignee:

Asustek Computer Inc., Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0245 (2013.01); H05K 1/0228 (2013.01); H05K 2201/09236 (2013.01);
Abstract

A circuit layout structure is provided. In the circuit layout structure, a transmission line group is disposed on a substrate. In its first differential signal transmission line pair, a first negative polarity transmission line is parallel to a first positive polarity transmission line and is configured to transmit a first negative polarity transmission signal of a first differential signal. In a second differential signal transmission line pair, a second positive polarity transmission line is parallel to a single-ended signal transmission line and is configured to transmit a second positive polarity transmission signal of a second differential signal. The second negative polarity transmission line is parallel to the second positive polarity transmission line. The single-ended signal transmission line is disposed between the first differential signal transmission line pair and the second differential signal transmission line pair.


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