The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
May. 15, 2018
Vertiv Tech Co., Ltd., Shenzhen, Guangdong, CN;
Vertiv Tech Co., Ltd., Shenzhen, CN;
Abstract
A current limiting control method for a three-level inverter, comprising the following steps: S. when a current output from a bridge arm is greater than or equal to a current limiting threshold and a received overcurrent signal is enabled, first turning off the main switch transistors and then turning off the auxiliary switch transistors; S. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors; S. when the received overcurrent signal is disabled and a next PWM effective edge of the main switch transistors arrives, turning on the main switch transistors. The present invention relates also to a current limiting control device for a three-level inverter. By implementing the present invention, it is possible to ensure voltage waveform quality and reduce switching loss.