The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Feb. 15, 2019
Psemi Corporation, San Diego, CA (US);
Antony Christopher Routledge, Basingstoke, GB;
pSemi Corporation, San Diego, CA (US);
Abstract
Circuits and methods for limiting excessive current in circuits (such as step-up DC-to-DC converter circuits) in which very low ohmic FETs (VLOFETs) are used in circuit pathways that are subjected to startup in-rush current. Embodiments include a current mirror driver circuit that can be coupled to the gates of a VLOFET to form a current mirror that limits current flow through the VLOFET. The current mirror driver circuit provides for pulsed operation so that a coupled VLOFET still toggles between an OFF state and a current limited mode, particularly during a startup period. By using the current mirror driver circuit in conjunction with VLOFETs in circuit pathways that are subjected to startup in-rush current, in-rush current can be regulated to an acceptable level. Notably, no additional impedances are required in circuit pathways that are subjected to startup in-rush current to limit in-rush current, thus avoiding loss of efficiency.