The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Dec. 27, 2017
Qualcomm Incorporated, San Diego, CA (US);
Mukul Gupta, Bangalore, IN;
Xiangdong Chen, San Diego, CA (US);
Ohsang Kwon, San Diego, CA (US);
Foua Vang, Anaheim, CA (US);
Stanley Seungchul Song, San Diego, CA (US);
Kern Rim, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.