The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Nov. 28, 2017
Applicant:

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Wuhan, Hubei, CN;

Inventors:

Yu Zhao, Hubei, CN;

Wonjoong Kim, Hubei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1345 (2006.01); H01L 49/02 (2006.01); H01L 23/60 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); G02F 1/13452 (2013.01); G02F 1/136204 (2013.01); G02F 1/136286 (2013.01); H01L 23/60 (2013.01); H01L 23/645 (2013.01); H01L 27/0266 (2013.01); H01L 27/0288 (2013.01); H01L 27/0296 (2013.01); H01L 27/124 (2013.01); H01L 27/1244 (2013.01); H01L 28/10 (2013.01); G02F 2001/13629 (2013.01);
Abstract

The present invention discloses an array substrate which includes a peripheral driving circuit region. The peripheral driving circuit includes a first metal layer, a first insulating layer and a second metal layer sequentially formed on a base substrate. There is a signal transmission line provided in the driving circuit region. The signal transmission line is connected in series with a current limiting unit. The current limiting unit includes M first metal lines formed in the first metal layer at intervals and N second metal lines formed in the second metal layer at intervals. The M first metal lines and the N second metal lines are alternately connected in series with each other through vias provided in the first insulating layer, and M and N are integers greater than 1, respectively. The present invention further comprises a display device including an array substrate mentioned above.


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