The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Apr. 18, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

James Raymond Maliclic Baello, Pampanga, PH;

Rafael Jose Lizares Guevara, Makati Metro Manila, PH;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01029 (2013.01);
Abstract

In a described example, an apparatus includes a semiconductor substrate and at least two pillar bumps formed on an active surface of the semiconductor substrate, the at least two pillar bumps extending away from the active surface and having ends spaced from the semiconductor substrate with solder material at the ends of the at least two pillar bumps. At least one spacer is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mount area on a first surface including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer. Mold compound covers the semiconductor substrate, the at least two pillars, the at least one spacer, and at least a portion of the semiconductor substrate.


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