The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

May. 03, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andre Schmenn, Sachsenkam, DE;

Damian Sojka, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/12 (2006.01); H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49805 (2013.01); H01L 21/4846 (2013.01); H01L 21/78 (2013.01); H01L 23/12 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/83 (2013.01); H01L 23/147 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16245 (2013.01);
Abstract

A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.


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