The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Jul. 03, 2018
Applicant:

Integra Technologies, Inc., El Segundo, CA (US);

Inventor:

Gabriele Formicone, Chandler, AZ (US);

Assignee:

Integra Technologies, Inc., El Segundo, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 23/34 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/492 (2006.01); H01L 29/16 (2006.01); H01L 29/73 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/34 (2013.01); H01L 23/481 (2013.01); H01L 23/492 (2013.01); H01L 23/49562 (2013.01); H01L 23/49894 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 23/642 (2013.01); H01L 24/48 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/73 (2013.01); H01L 29/778 (2013.01); H01L 2224/48157 (2013.01); H01L 2224/48177 (2013.01); H01L 2224/48195 (2013.01);
Abstract

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.


Find Patent Forward Citations

Loading…