The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Apr. 23, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Dongwoo Han, Seoul, KR;

Kwang-Yong Yang, Seoul, KR;

Jinwook Lee, Seoul, KR;

Kyungyub Jeon, Yongin-si, KR;

Haegeon Jung, Yongin-si, KR;

Dohyoung Kim, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/30604 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.


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