The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Feb. 28, 2017
Applicant:

Surecore Limited, Leeds, GB;

Inventors:

Stefan Cosemans, Leeds, GB;

Bram Rooseleer, Leeds, GB;

Assignee:

SURECORE LIMITED, Sheffield, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 7/22 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/062 (2013.01); G11C 7/065 (2013.01); G11C 7/067 (2013.01); G11C 7/08 (2013.01); G11C 7/1072 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 7/22 (2013.01); G11C 8/16 (2013.01); G11C 2207/005 (2013.01);
Abstract

There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.


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