The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Sep. 14, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, Sichuan, CN;

Inventors:

Bo Wu, Beijing, CN;

Wen Tan, Beijing, CN;

Zhenxiao Tong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 5/00 (2006.01); G09G 3/20 (2006.01); G11C 19/18 (2006.01); G11C 19/28 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 5/003 (2013.01); G09G 3/20 (2013.01); G11C 19/184 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G11C 19/28 (2013.01);
Abstract

A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input and set circuit, connected with a pull-up node; a storage circuit, connected with the pull-up node and an output end respectively; an output circuit, configured to provide a second clock signal to the output end when a voltage of the pull-up node satisfies an output condition; and a first pull-down circuit, configured to provide a first power voltage to the output end when a first pull-down condition is satisfied. The input and set circuit is further configured to: in a set stage of forward scanning or an input stage of reverse scanning, receive a third clock signal and a second input signal, and in response to the third clock signal, write a voltage of the second input signal into the pull-up node.


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