The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Aug. 26, 2016
Applicants:

Guangzhou Fastprint Circuit Tech Co., Ltd., Guangzhou, CN;

Shenzhen Fastprint Circuit Tech Co., Ltd., Shenzhen, CN;

Inventors:

Zhirui Liu, Guangzhou, CN;

Zhongyu Mao, Guangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5045 (2013.01);
Abstract

Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components. With regard to the condition where a pin connection relationship of an element does not change but a network name changes, occurring during the conversion of different pieces of EDA software, and the present disclosure can effectively guarantee the accuracy of a connection after a schematic diagram and a PCB network are converted. The present disclosure can be widely applied to netlist comparison systems of pin connection relationships of various EDA software components.


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