The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Mar. 03, 2017
Applicant:

Wave Computing, Inc., Campbell, CA (US);

Inventors:

Christopher John Nicol, Campbell, CA (US);

Samit Chaudhuri, Cupertino, CA (US);

Radoslav Danilak, Cupertino, CA (US);

Assignee:

Wave Computing, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2018.01); G06F 15/17 (2006.01); G06F 15/76 (2006.01); G06F 13/42 (2006.01); G06F 1/32 (2019.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 9/30 (2018.01); G06F 9/4401 (2018.01); G06F 9/38 (2018.01); G06F 15/173 (2006.01); G06F 15/82 (2006.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3891 (2013.01); G06F 9/4418 (2013.01); G06F 13/4068 (2013.01); G06F 15/17 (2013.01); G06F 1/324 (2013.01); G06F 9/381 (2013.01); G06F 9/3814 (2013.01); G06F 9/3869 (2013.01); G06F 13/4059 (2013.01); G06F 13/423 (2013.01); G06F 15/17362 (2013.01); G06F 15/825 (2013.01);
Abstract

A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.


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