The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Feb. 21, 2019
Oracle International Corporation, Redwood Shores, CA (US);
Xianda Ma, Cupertino, CA (US);
Michael David Derbish, Pleasanton, CA (US);
Cornelia Luise Edeltraut Koch-Stoschek, Palo Alto, CA (US);
Rambabu Lolabattu, San Jose, CA (US);
Simon yiu hoi Poon, San Jose, CA (US);
Cheng Yang, Cupertino, CA (US);
Oracle International Corporation, Redwood Shores, CA (US);
Abstract
Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a 'black box' regarding FPGA I/O during the occurrence of the catastrophic events within the system.