The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Oct. 06, 2017
Imec Vzw, Leuven, BE;
Stichting Imec Nederland, Eindhoven, BE;
Universidad Complutense DE Madrid, Madrid, ES;
Francky Catthoor, Temse, BE;
Matthias Hartmann, Kessel-Lo, BE;
Jose Ignacio Gomez, Madrid, ES;
Christian Tenllado, Madrid, ES;
Sotiris Xydis, Athens, GR;
Javier Setoain Rodrigo, Madrid, ES;
Thomas Papastergiou, Athens, GR;
Christos Baloukas, Athens, GR;
Anup Kumar Das, Eindhoven, NL;
Dimitrios Soudris, Athens, GR;
Imec vzw, Leuven, BE;
Stitching Imec Nederland, Eindhoven, NL;
Universidad Complutense de Madrid, Madrid, ES;
Abstract
The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.