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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10592219 B1

PDFFull Text
Date of Patent:
Mar. 17, 2020

Filed:

Aug. 22, 2018

Computer system and method for parallel program code optimization and deployment

Applicant:

Karlsruhe Institute of Technology, Karlsruhe, DE;

Inventors:

Oliver Oey, Karlsruhe, DE;

Timo Stripf, Karlsruhe, DE;

Michael Rückauer, Karlsruhe, DE;

Jürgen Becker, Jockgrim, DE;

Assignee:

Karlsruhe Institute of Technology, Karlsruhe, DE;

Attorney:

Brake Hughes Bellermann LLP

Primary Examiner:

Anibal Rivera

Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/44 (2018.01); G06F 9/50 (2006.01); G06F 17/50 (2006.01); G06F 8/41 (2018.01); G06F 8/60 (2018.01); G06F 9/48 (2006.01); G06F 8/72 (2018.01);
U.S. Cl.
CPC ...
G06F 8/456 (2013.01); G06F 8/443 (2013.01); G06F 8/451 (2013.01); G06F 8/453 (2013.01); G06F 8/458 (2013.01); G06F 8/60 (2013.01); G06F 8/427 (2013.01); G06F 8/72 (2013.01); G06F 9/4881 (2013.01); G06F 9/5088 (2013.01);
Abstract

A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.

Find Patent Forward Citations

Oey, Oliver. (2020). Computer system and method for parallel program code optimization and deployment (U.S. Patent No. 10592219). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10592219

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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