The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Oct. 17, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David Paulsen, Inver Grove Heights, MN (US);

Phil Paone, Rochester, MN (US);

George Paulik, Rochester, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Karl Erickson, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/487 (2006.01); H03K 19/20 (2006.01); H03M 1/20 (2006.01); H03G 3/00 (2006.01);
U.S. Cl.
CPC ...
G06F 7/4876 (2013.01); H03G 3/001 (2013.01); H03K 19/20 (2013.01); H03M 1/206 (2013.01); G06F 2207/482 (2013.01);
Abstract

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.


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