The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
May. 10, 2019
International Business Machines Corporation, Armonk, NY (US);
David Paulsen, Inver Grove Heights, MN (US);
Phil Paone, Rochester, MN (US);
John E. Sheets, II, Zumbrota, MN (US);
George Paulik, Rochester, MN (US);
Karl Erickson, Rochester, MN (US);
Gregory J. Uhlmann, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number 'n.' The adder circuit includes sets of scaled capacitors, each capacitor connected to an ninput of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2*a unit capacitance (C). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.