The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Sep. 26, 2018
Applicant:

Sensor Electronic Technology, Inc., Columbia, SC (US);

Inventors:

Grigory Simin, Columbia, SC (US);

Michael Shur, Latham, NY (US);

Alexander Dobrinsky, Loudonville, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 33/24 (2010.01); H01L 33/06 (2010.01); H01L 33/08 (2010.01); H01L 33/14 (2010.01); H01L 33/20 (2010.01); H01L 33/32 (2010.01); H01L 33/40 (2010.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 33/24 (2013.01); H01L 33/06 (2013.01); H01L 33/08 (2013.01); H01L 33/14 (2013.01); H01L 33/20 (2013.01); H01L 33/32 (2013.01); H01L 33/405 (2013.01); H01L 33/44 (2013.01); H01L 2933/0091 (2013.01);
Abstract

An opto-electronic device with two-dimensional injection layers is described. The device can include a semiconductor structure with a semiconductor layer having one of an n-type semiconductor layer or a p-type semiconductor layer, and a light generating structure formed on the semiconductor layer. A set of tilted semiconductor heterostructures is formed over the semiconductor structure. Each tilted semiconductor heterostructure includes a core region, a set of shell regions adjoining a sidewall of the core region, and a pair of two-dimensional carrier accumulation (2DCA) layers. Each 2DCA layer is formed at a heterointerface between one of the sidewalls of the core region and one of the shell regions. The sidewalls of the core region, the shell regions, and the 2DCA layers each having a sloping surface, wherein each 2DCA layer forms an angle with a surface of the semiconductor structure.


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