The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jul. 27, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tomoo Hishida, Yokohama, JP;

Yoshihisa Iwata, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11582 (2017.01); G11C 5/06 (2006.01); G11C 8/12 (2006.01); G11C 7/18 (2006.01); G11C 5/02 (2006.01); H01L 27/10 (2006.01); H01L 23/528 (2006.01); H01L 27/11575 (2017.01); H01L 29/792 (2006.01); H01L 27/11568 (2017.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/18 (2013.01); G11C 8/12 (2013.01); G11C 16/0483 (2013.01); H01L 23/528 (2013.01); H01L 27/10 (2013.01); H01L 27/11568 (2013.01); H01L 27/11575 (2013.01); H01L 29/7926 (2013.01); G11C 5/04 (2013.01); G11C 2213/71 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.


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