The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
Dec. 20, 2018
International Business Machines Corporation, Armonk, NY (US);
Oleg Gluschenkov, Tannersville, NY (US);
Jiseok Kim, Allentown, PA (US);
Zuoguang Liu, Schenectady, NY (US);
Shogo Mochizuki, Clifton Park, NY (US);
Hiroaki Niimi, Cohoes, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile