The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
Sep. 15, 2017
Applicant:
Chip Solutions, Llc, Phoenix, AZ (US);
Inventor:
Sukianto Rusli, Phoenix, AZ (US);
Assignee:
Chip Solutions, LLC, Phoenix, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/67 (2006.01); H01L 23/13 (2006.01); H01L 21/673 (2006.01); H01L 21/48 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/673 (2013.01); H01L 21/67242 (2013.01); H01L 21/6835 (2013.01); H01L 22/20 (2013.01); H01L 22/30 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/49816 (2013.01); H01L 23/5226 (2013.01); H01L 24/08 (2013.01); H01L 24/17 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 23/3128 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08501 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/821 (2013.01); H01L 2224/82896 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/15747 (2013.01);
Abstract
Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.