The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jul. 09, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Young-Min Ko, Hwaseong-si, KR;

Hyuk Woo Kwon, Seoul, KR;

Jun-Won Lee, Asan-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); G03F 7/20 (2006.01); H01L 21/033 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3081 (2013.01); G03F 7/70033 (2013.01); H01L 21/02115 (2013.01); H01L 21/033 (2013.01); H01L 21/31144 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01);
Abstract

Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.


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