The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Dec. 21, 2018
Applicant:

Shanghai Avic Opto Electronics Co.,ltd., Shanghai, CN;

Inventors:

Rili Fei, Shanghai, CN;

Zhiqiang Xia, Shanghai, CN;

Dandan Qin, Shanghai, CN;

Dongliang Dun, Shanghai, CN;

Shoufu Jian, Shanghai, CN;

Tinghai Wang, Shanghai, CN;

Ying Xie, Shanghai, CN;

Houxun Xia, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/28 (2006.01); G09G 3/20 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G11C 19/287 (2013.01); G06F 3/0416 (2013.01); G09G 3/20 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.


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