The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Nov. 30, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Harsh N. Patel, Clifton Park, NY (US);

Bipul C. Paul, Mechanicville, NY (US);

Joseph Versaggi, Galway, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 5/14 (2006.01); H01L 45/00 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 5/145 (2013.01); G11C 11/161 (2013.01); G11C 11/1655 (2013.01); G11C 11/1697 (2013.01); G11C 13/0026 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 45/12 (2013.01); H01L 45/16 (2013.01);
Abstract

Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.


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