The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Aug. 17, 2018
Applicant:

Japan Display Inc., Minato-ku, JP;

Inventors:

Hiroyuki Abe, Minato-ku, JP;

Kentaro Agata, Minato-ku, JP;

Assignee:

Japan Display Inc., Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/00 (2006.01); G09G 3/3225 (2016.01); G09G 3/36 (2006.01); G02F 1/1345 (2006.01); H01L 27/32 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G09G 3/006 (2013.01); G02F 1/13452 (2013.01); G02F 1/136286 (2013.01); G09G 3/3225 (2013.01); G09G 3/3648 (2013.01); H01L 27/3276 (2013.01); G02F 1/1368 (2013.01); G02F 2001/13685 (2013.01); G09G 2330/12 (2013.01);
Abstract

An inspection circuit is properly protected in a display device, which the driver IC is not on the terminal area. A liquid crystal display device comprising a TFT substrate having a display area, in which video signal lines are formed, and a terminal area; a counter substrate overlapping with the display area of the TFT substrate; the counter substrate and the TFT substrate are adhered by the seal material, the display area is formed in an area surrounded by the seal material; wherein the flexible wiring circuit substrate connects to the terminal area, the driver IC, which supplies video signals to the video signal lines, is not installed in the terminal area, the inspection circuit is formed between the display area and the terminal area, wherein the inspection circuit overlaps with the counter substrate in a plan view.


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