The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jun. 22, 2015
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Nishanth Sinnadurai, Scarborough, CA;

Benjamin Gamsa, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 17/5054 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); G06F 2217/84 (2013.01);
Abstract

A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.


Find Patent Forward Citations

Sinnadurai, Nishanth. (2020). Method and apparatus for utilizing estimations for register retiming in a design compilation flow (U.S. Patent No. 10586004). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10586004

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…