The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jun. 26, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Erez Barak, Kfar Saba, IL;

Giora Biran, Zichron-Yaakov, IL;

Amir Turi, Ramat Gan, IL;

Osher Yifrach, Modiin, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 17/50 (2006.01); G06F 1/10 (2006.01); G06F 1/3287 (2019.01); G06F 1/3203 (2019.01); G06F 1/3228 (2019.01); G06F 1/324 (2019.01); G06F 11/34 (2006.01); G06F 1/329 (2019.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 1/10 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3228 (2013.01); G06F 1/3287 (2013.01); G06F 11/3409 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01); G06F 1/329 (2013.01); G06F 9/3869 (2013.01); G06F 2217/02 (2013.01); G06F 2217/62 (2013.01); G06F 2217/68 (2013.01); G06F 2217/78 (2013.01); G06F 2217/84 (2013.01);
Abstract

Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.


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