The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
May. 15, 2017
Fine-grained analog memory device based on charge-trapping in high-k gate dielectrics of transistors
Applicant:
The Regents of the University of California, Oakland, CA (US);
Inventors:
Xuefeng Gu, Los Angeles, CA (US);
Subramanian S. Iyer, Los Angeles, CA (US);
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Oakland, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G11C 11/54 (2006.01); G06F 7/02 (2006.01); H01L 29/792 (2006.01); G11C 27/00 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 7/023 (2013.01); G06N 3/0635 (2013.01); G11C 11/54 (2013.01); G11C 16/0466 (2013.01); G11C 27/005 (2013.01); H01L 29/792 (2013.01);
Abstract
A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.