The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Nov. 13, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Keshav G. Kamble, Fremont, CA (US);

Jayakrishna Kidambi, San Jose, CA (US);

Vijoy A. Pandey, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 28/08 (2009.01); H04W 40/02 (2009.01); H04L 12/18 (2006.01); H04L 12/741 (2013.01); G06F 9/455 (2018.01); H04L 12/46 (2006.01); H04L 29/06 (2006.01); H04L 12/721 (2013.01); H04L 12/931 (2013.01); H04L 29/12 (2006.01);
U.S. Cl.
CPC ...
H04W 28/08 (2013.01); G06F 9/45533 (2013.01); G06F 9/45558 (2013.01); H04L 12/18 (2013.01); H04L 12/46 (2013.01); H04L 12/4641 (2013.01); H04L 45/66 (2013.01); H04L 45/74 (2013.01); H04L 69/00 (2013.01); H04L 69/18 (2013.01); H04W 40/02 (2013.01); G06F 2009/45595 (2013.01); H04L 12/4633 (2013.01); H04L 29/12028 (2013.01); H04L 49/70 (2013.01);
Abstract

In one embodiment, a system includes a plurality of network ports including multiple Peripheral Component Interconnect express (PCIe) ports, a network interface card (NIC) driver configured to interface with and support an accelerated NIC, a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to provide a virtual switch to host one or more virtual machines (VMs). Also, the logic is configured to cause the processor to provide a hypervisor which processes at least some outbound packets received from the one or more VMs and processes at least some inbound packets sent to the one or more VMs. Moreover, the logic is configured to cause the processor to divert network traffic of the one or more VMs that has overlay functionality provided by the accelerated NIC to bypass the hypervisor.


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