The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jul. 24, 2017
Applicants:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Lei Zhang, Richmond Hill, CA;

Sateesh Lagudu, Hyderabad, IN;

Allen Rush, Danville, CA (US);

Razvan Dan-Dobre, Toronto, CA;

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI Technologies ULC, Markham, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 21/4143 (2011.01); G06F 3/14 (2006.01); H04N 7/14 (2006.01); H04N 7/15 (2006.01); H04N 19/172 (2014.01); H04N 19/90 (2014.01); H04N 21/418 (2011.01); H04N 19/42 (2014.01); G06T 9/00 (2006.01);
U.S. Cl.
CPC ...
H04N 21/4143 (2013.01); G06F 3/14 (2013.01); H04N 7/141 (2013.01); H04N 7/147 (2013.01); H04N 7/15 (2013.01); H04N 19/172 (2014.11); H04N 19/42 (2014.11); H04N 19/90 (2014.11); H04N 21/4183 (2013.01); G06T 9/007 (2013.01); G09G 2340/02 (2013.01);
Abstract

Systems, apparatuses, and methods for integrating a video codec with an inference engine are disclosed. A system is configured to implement an inference engine and a video codec while sharing at least a portion of its processing elements between the inference engine and the video codec. By sharing processing elements when combining the inference engine and the video codec, the silicon area of the combination is reduced. In one embodiment, the portion of processing elements which are shared include a motion prediction/motion estimation/MACs engine with a plurality of multiplier-accumulator (MAC) units, an internal memory, and peripherals. The peripherals include a memory interface, a direct memory access (DMA) engine, and a microprocessor. The system is configured to perform a context switch to reprogram the processing elements to switch between operating modes. The context switch can occur at a frame boundary or at a sub-frame boundary.


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