The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Oct. 12, 2018
Applicant:

Avnera Corporation, Beaverton, OR (US);

Inventors:

Jianping Wen, Beaverton, OR (US);

Garry Link, Pacific City, OR (US);

Wai Laing Lee, Austin, TX (US);

Assignee:

Avnera Corporation, Beaverton, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/40 (2006.01); H03M 1/46 (2006.01); H03M 1/38 (2006.01); H03M 1/80 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/0692 (2013.01); H03M 1/38 (2013.01); H03M 1/403 (2013.01); H03M 1/462 (2013.01); H05K 999/99 (2013.01); H03M 1/0682 (2013.01); H03M 1/468 (2013.01); H03M 1/804 (2013.01);
Abstract

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port.


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