Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power

Abstract

A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.