The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jun. 28, 2019
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Nenad Pavlovic, Eindhoven, NL;

Vladislav Dyachenko, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03L 7/089 (2006.01); H03L 7/087 (2006.01); H03M 1/46 (2006.01); G04F 10/00 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0895 (2013.01); G04F 10/005 (2013.01); H03L 7/087 (2013.01); H03L 7/0992 (2013.01); H03M 1/466 (2013.01); G06F 1/10 (2013.01); H03L 2207/50 (2013.01);
Abstract

Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.


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