The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jul. 19, 2018
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventor:

SeungMin Lee, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 27/32 (2006.01); G09G 3/3291 (2016.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78648 (2013.01); G09G 3/3291 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01); G09G 2310/08 (2013.01); H01L 29/78696 (2013.01);
Abstract

Disclosed are a thin film transistor and a display device including the thin film transistor. The thin film transistor comprises: a bottom gate electrode on a substrate; a semiconductor layer overlapping with the bottom gate electrode, wherein the semiconductor layer comprises a N-type semiconductor layer and a P-type semiconductor layer, and the N-type semiconductor layer is overlapped partly with the P-type semiconductor layer; a first source electrode and a first drain electrode respectively connected to the P-type semiconductor layer; a second source electrode and a second drain electrode respectively connected to a portion of the N-type semiconductor layer which is not overlapped with the P-type semiconductor layer; and a top gate electrode above the semiconductor layer. According to the embodiment of the present disclosure, a complexity of a manufacturing process of the thin film transistor is reduced.


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