The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jul. 26, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

Bartlomiej J. Pawlak, Leuven, BE;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); B82Y 10/00 (2011.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); B82Y 10/00 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/1083 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66772 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01); H01L 29/165 (2013.01);
Abstract

Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.


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