The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2020
Filed:
Sep. 26, 2018
Applicant:
Sumitomo Electric Industries, Ltd., Osaka, JP;
Inventor:
Ken Nakata, Osaka, JP;
Assignee:
SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 21/465 (2006.01); H01L 21/443 (2006.01); H01L 21/027 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/02057 (2013.01); H01L 21/0262 (2013.01); H01L 21/0273 (2013.01); H01L 21/02178 (2013.01); H01L 21/02189 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02576 (2013.01); H01L 21/02631 (2013.01); H01L 21/02636 (2013.01); H01L 21/30621 (2013.01); H01L 21/443 (2013.01); H01L 21/465 (2013.01); H01L 29/0891 (2013.01); H01L 29/1029 (2013.01); H01L 29/267 (2013.01); H01L 29/66462 (2013.01); H01L 29/66969 (2013.01); H01L 29/7786 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01); H01L 21/823418 (2013.01); H01L 29/0843 (2013.01); H01L 29/2003 (2013.01); H01L 29/45 (2013.01); H01L 29/66636 (2013.01); H01L 29/78681 (2013.01);
Abstract
A process of forming a field effect transistor (FET) and a FET are disclosed. The process includes steps of forming a nitride semiconductor layer on a substrate; selectively growing an n-region made of oxide semiconductor material on the nitride semiconductor layer and subsequently depositing oxide film on the n-region; rinsing the oxide film with an acidic solution; forming an opening in the oxide film to expose the oxide semiconductor layer therein; and depositing a metal within the opening such that the metal is in direct contact with the n-region.